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? semiconductor components industries, llc, 2002 april, 2002 rev. 7 1 publication order number: mc10e445/d mc10e445, mc100e445 5vecl 4bit serial/parallel converter the mc10/100e445 is an integrated 4-bit serial to parallel data converter. the device is designed to operate for nrz data rates of up to 2.0 gb/s. the chip generates a divide by 4 and a divide by 8 clock for both 4-bit conversion and a two chip 8-bit conversion function. the conversion sequence was chosen to convert the first serial bit to q0, the second to q1 etc. two selectable serial inputs provide a loopback capability for testing purposes when the device is used in conjunction with the e446 parallel to serial converter. the start bit for conversion can be moved using the sync input. a single pulse applied asynchronously for at least two input clock cycles shifts the start bit for conversion from qn to qn1. for each additional shift required an additional pulse must be applied to the sync input. asserting the sync input will force the internal clock dividers to aswallowo a clock pulse, effectively shifting a bit from the qn to the qn1 output (see timing diagram b). the mode input is used to select the conversion mode of the device. with the mode input low, or open, the device will function as a 4-bit converter. when the mode input is driven high the data on the output will change on every eighth clock cycle thus allowing for an 8-bit conversion scheme using two e445's. when cascaded in an 8-bit conversion scheme the devices will not operate at the 2.0 gb/s data rate of a single device. refer to the applications section of this data sheet for more information on cascading the e445. upon power-up the internal flip-flops will attain a random state. to synchronize multiple e445's in a system the master reset must be asserted. the v bb pin, an internally generated voltage supply, is available to this device only. for single-ended input conditions, the unused differential input is connected to v bb as a switching reference voltage. v bb may also rebias ac coupled inputs. when used, decouple v bb and v cc via a 0.01 f capacitor and limit current sourcing or sinking to 0.5 ma. when not used, v bb should be left open. the 100 series contains temperature compensation. ? on-chip clock 4 and 8 ? 2.0 gb/s data rate capability ? differential clock and serial inputs ? v bb output for single-ended input applications ? asynchronous data synchronization ? mode select to expand to 8-bits ? pecl mode operating range: v cc = 4.2 v to 5.7 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 4.2 v to 5.7 v ? internal input pulldown resistors ? esd protection: > 2 kv hbm, > 100 v mm ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8 , oxygen index 28 to 34 ? transistor count = 528 devices device package shipping ordering information mc10e445fn plcc28 37 units/rail mc10e445fnr2 plcc28 500 units/reel mc100e445fn plcc28 37 units/rail mc100e445fnr2 plcc28 500 units/reel marking diagrams a = assembly location wl = wafer lot yy = year ww = work week plcc28 fn suffix case 776 mc10e445fn awlyyww mc100e445fn awlyyww 128 128 http://onsemi.com
mc10e445, mc100e445 http://onsemi.com 2 pin description pin function sina, sina sinb, sinb sel q0q3 clk, clk cl/4, cl/4 cl/8, cl/8 mode synch v bb v cc , v cco v ee nc ecl differential serial data input a ecl differential serial data input b ecl serial input selector pin ecl parallel data outputs ecl differential clock inputs ecl differential 4 clock output ecl differential 8 clock output ecl conversion mode 4-bit/8-bit ecl conversion synchronizing input reference voltage output positive supply negative supply no connect function tables mode conversion sel serial input l h 4-bit 8-bit h l a b q d sinb q3 sout sout cl/4 cl/4 cl/8 cl/8 sinb sina sina clk clk mode reset sync sel q d q d q2 q d q d q1 q d q d q0 q d 1 0 4 r out 2 r out latch en out in q d q d v bb figure 2. logic diagram v cco nc mode sina sina q3 v cco cl/4 cl/4 v cco cl/8 cl/8 sout sout v cc q0 q1 v cco q2 sinb sinb sel v ee clk clk v bb 18 17 16 15 14 13 12 19 20 21 22 23 24 25 11 10 9 8 7 6 5 26 27 28 1 2 3 4 pinout: 28-lead plcc (top view) reset sync * all v cc and v cco pins are tied together on the die. warning: all v cc , v cco , and v ee pins must be externally connected to power supply to guarantee proper operation. figure 1. pinout assignment
mc10e445, mc100e445 http://onsemi.com 3 maximum ratings (note 1) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 v v ee necl mode power supply v cc = 0 v 8 v v i pecl mode input voltage v ee = 0 v v i v cc 6 v v i pecl mode in ut voltage necl mode input voltage v ee 0 v v cc = 0 v v i ? ?? ? ? v ee 6 6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma ta operating temperature range 0 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junctiontoambient) 0 lfpm 500 lfpm 28 plcc 28 plcc 63.5 43.5 c/w c/w q jc thermal resistance (junctiontocase) std bd 28 plcc 22 to 26 c/w v ee pecl operating range necl operating range 4.2 to 5.7 5.7 to 4.2 v v t sol wave solder < 2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur. 10e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 2) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 154 185 154 185 154 185 ma v oh output high voltage (note 3) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mv voh sout output high voltage sout/sout 3975 4170 3975 4170 3975 4170 mv v ol output low voltage (note 3) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mv v ih input high voltage (singleended) 3830 3995 4160 3870 4030 4190 3940 4110 4280 mv v il input low voltage (singleended) 3050 3285 3520 3050 3285 3520 3050 3302 3555 mv v bb output voltage reference 3.62 3.63 3.65 3.75 3.69 3.81 v v ihcmr input high voltage common mode range (differential) (note 4) 2.2 4.6 2.2 4.6 2.2 4.6 v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 2. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.06 v. 3. outputs are terminated through a 50 w resistor to v cc 2 volts. 4. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . 10e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 5) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 154 185 154 185 154 185 ma v oh output high voltage (note 6) 1020 930 840 980 895 810 910 815 720 mv voh sout output high voltage sout/sout 1025 830 1025 830 1025 830 mv v ol output low voltage (note 6) 1950 1790 1630 1950 1790 1630 1950 1773 1595 mv v ih input high voltage (singleended) 1170 1005 840 1130 970 810 1060 890 720 mv v il input low voltage (singleended) 1950 1715 1480 1950 1715 1480 1950 1698 1445 mv v bb output voltage reference 1.38 1.37 1.35 1.25 1.31 1.19 v v ihcmr input high voltage common mode range (differential) (note 7) 2.8 0.4 2.8 0.4 2.8 0.4 v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.065 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 5. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.06 v. 6. outputs are terminated through a 50 w resistor to v cc 2 volts. 7. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc .
mc10e445, mc100e445 http://onsemi.com 4 100e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 8) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 154 185 154 185 177 212 ma v oh output high voltage (note 9) 3975 4050 4120 3975 4050 4120 3975 4050 4120 mv voh sout output high voltage sout/sout 3975 4170 3975 4170 3975 4170 mv v ol output low voltage (note 9) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mv v ih input high voltage (singleended) 3835 4050 4120 3835 4120 4120 3835 4120 4120 mv v il input low voltage (singleended) 3190 3300 3525 3190 3525 3525 3190 3525 3525 mv v bb output voltage reference 3.62 3.74 3.62 3.74 3.62 3.74 v v ihcmr input high voltage common mode range (differential) (note 10) 2.2 4.6 2.2 4.6 2.2 4.6 v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 8. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 9. outputs are terminated through a 50 w resistor to v cc 2 volts. 10. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc . 100e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 11) 0 c5 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 154 185 154 185 177 212 ma v oh output high voltage (note 12) 1025 950 880 1025 950 880 1025 950 880 mv voh sout output high voltage sout/sout 1025 830 1025 830 1025 830 mv v ol output low voltage (note 12) 1810 1705 1620 1810 1745 1620 1810 1740 1620 mv v ih input high voltage (singleended) 1165 950 880 1165 880 880 1165 880 880 mv v il input low voltage (singleended) 1810 1700 1475 1810 1475 1475 1810 1475 1475 mv v bb output voltage reference 1.38 1.26 1.38 1.26 1.38 1.26 v v ihcmr input high voltage common mode range (differential) (note 13) 2.8 0.4 2.8 0.4 2.8 0.4 v i ih input high current 150 150 150 m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 11. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 12. outputs are terminated through a 50 w resistor to v cc 2 volts. 13. v ihcmr min varies 1:1 with v ee , max varies 1:1 with v cc .
mc10e445, mc100e445 http://onsemi.com 5 ac characteristics v ccx = 5.0 v; v ee = 0.0 v or v ccx = 0.0 v; v ee = 5.0 v (note 14) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum conversion frequency 2.0 2.0 2.0 gb/s nrz t plh t phl propagation delay to output clk to q, reset to q clk to sout (diff) clk to cl/4(diff) clk to cl/8(diff) 1500 800 1100 1100 1800 975 1325 1325 2100 1150 1550 1550 1500 800 1100 1100 1800 975 1325 1325 2100 1150 1550 1550 1500 800 1100 1100 1800 975 1325 1325 2100 1150 1550 1550 ps t s setup time sina, sinb sel 100 0 250 200 100 0 250 200 100 0 250 200 ps t h hold time sina, sinb, sel 450 300 450 300 450 300 ps t rr reset recovery time 500 300 500 300 500 300 ps t pw minimum pulse width clk, mr 400 400 400 ps t jitter cycletocycle jitter tbd tbd tbd ps t r t f rise/fall times 20%80% sout other 100 200 225 425 350 650 100 200 225 425 350 650 100 200 225 425 350 650 ps 14. 10 series: v ee can vary +0.46 v / 0.06 v. 100 series: v ee can vary +0.46 v / 0.8 v. reset cl4 / cl4 cl8 / cl8 t rr figure 3.
mc10e445, mc100e445 http://onsemi.com 6 timing diagram a. 1:4 serial to parallel conversion dn4 dn3 dn2 dn1 dn dn+1 dn+2 dn+3 dn4 dn3 dn2 dn1 dn dn+1 dn+2 dn+3 dn4 dn3 dn2 dn1 dn dn+1 dn+2 dn+3 clk sin reset q0 q1 q2 q3 sout cl/4 cl/8 dn4 dn3 dn2 dn1 dn+1 dn+2 dn+3 dn+4 dn4 dn3 dn2 dn1 dn dn+1 dn+2 dn+3 dn4 dn3 dn2 dn1 dn dn+1 dn+2 dn+3 clk sin reset q0 q1 q2 q3 sout cl/4 cl/8 sync timing diagram b. 1:4 serial to parallel conversion with sync pulse dn+4 dn+4 figure 4. timing diagrams
mc10e445, mc100e445 http://onsemi.com 7 applications information the mc10e/100e445 is an integrated 1:4 serial to parallel converter. the chip is designed to work with the e446 device to provide both transmission and receiving of a high speed serial data path. the e445, can convert up to a 2.0gb/s nrz data stream into 4-bit parallel data. the device also provides a divide by four clock output to be used to synchronize the parallel data with the rest of the system. the e445 features multiplexed dual serial inputs to provide test loop capability when used in conjunction with the e446. figure 5 illustrates the loop test architecture. the architecture allows for the electrical testing of the link without requiring actual transmission over the serial data path medium. the sina serial input of the e445 has an extra buffer delay and thus should be used as the loop back serial input. sinb sinb sina sina sout sout parallel data parallel data to serial medium from serial medium figure 5. loopback test architecture the e445 features a differential serial output and a divide by 8 clock output to facilitate the cascading of two devices to build a 1:8 demultiplexer. figure 6 illustrates the architecture for a 1:8 demultiplexer using two e445's; the timing diagram for this configuration can be found on the following page. notice the serial outputs (sout) of the lower order converter feed the serial inputs of the the higher order device. this feed through of the serial inputs bounds the upper end of the frequency of operation. the clock to serial output propagation delay plus the setup time of the serial input pins must fit into a single clock period for the cascade architecture to function properly. using the worst case values for these two parameters from the data sheet, tpd clk to sout = 1150ps and ts for sin = 100ps, yields a minimum period of 1050ps or a clock frequency of 950mhz. the clock frequency is significantly lower than that of a single converter, to increase this frequency some games can be played with the clock input of the higher order e445. by delaying the clock feeding the second e445 relative to the clock of the first e445 the frequency of operation can be increased. the delay between the two clocks can be increased until the minimum delay of clock to serial out would potentially cause a serial bit to be swallowed (figure 7). q3 q7 q2 q6 q1 q5 q0 q4 sin sin sout sout e445a q3 q3 q2 q2 q1 q1 q0 q0 sin sin e445b clock clock serial input data parallel output data 800ps 1150ps 100p s clock t pd clk to sout figure 6. cascaded 1:8 converter architecture with a minimum delay of 800ps on this output the clock for the lower order e445 cannot be delayed more than 800ps relative to the clock of the first e445 without potentially missing a bit of information. because the setup time on the serial input pin is negative coincident excursions on the data and clock inputs of the e445 will result in correct operation. figure 7. cascade frequency limitation 800ps 1150ps clock b t pd clk to sout clock a perhaps the easiest way to delay the second clock relative to the first is to take advantage of the dif ferential clock inputs of the e445. by connecting the clock for the second e445 to the complimentary clock input pin the device will clock a half a clock period after the first e445 (figure 8). utilizing this simple technique will raise the potential conversion frequency up to 1.4ghz. the divide by eight clock of the second e445 should be used to synchronize the parallel data to the rest of the system as the parallel data of the two e445's will no longer be synchronized. this skew problem between the outputs can be worked around as the parallel information will be static for eight more clock pulses.
mc10e445, mc100e445 http://onsemi.com 8 figure 8. extended frequency 1:8 demultiplexer 800ps 1150ps clock b t pd clk to sout clock a 700ps (1.4ghz) 100ps q3 q7 q2 q6 q1 q5 q0 q4 sin sin sout sout e445a q3 q3 q2 q2 q1 q1 q0 q0 sin sin e445b clock clock serial input data parallel output data figure 9. timing diagram a. 1:8 serial to parallel conversion dn4 dn3 dn2 dn1 dn dn+1 dn+2 dn+3 dn4 dn3 dn2 dn1 dn dn+1 dn+2 dn+3 dn4 dn3 dn2 dn1 dn dn+1 dn+2 dn+3 clk sina q0 q1 q2 q3 q4 (q0 a) q5 (q1 a) dn4 dn3 dn2 dn1 dn dn+1 q6 (q2 a) q7 (q3 a) souta soutb cl/4a cl/4b cl/8a cl/8b
mc10e445, mc100e445 http://onsemi.com 9 typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device qd 50 50 v tt q d v tt = v cc 2.0 v resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc10e445, mc100e445 http://onsemi.com 10 package dimensions plcc28 fn suffix plastic plcc package case 77602 issue e n m l v w d d y brk 28 1 view s s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s l-m m 0.007 (0.180) n s t t b s l-m s 0.010 (0.250) n s t s l-m m 0.007 (0.180) n s t u s l-m m 0.007 (0.180) n s t z g1 x view dd s l-m m 0.007 (0.180) n s t k1 view s h k f s l-m m 0.007 (0.180) n s t notes: 1. datums -l-, -m-, and -n- determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 --- 0.51 --- k 0.025 --- 0.64 --- r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y --- 0.020 --- 0.50 z 2 10 2 10 g1 0.410 0.430 10.42 10.92 k1 0.040 --- 1.02 ---
mc10e445, mc100e445 http://onsemi.com 11 notes
mc10e445, mc100e445 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10e445/d north america literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com fax response line: 3036752167 or 8003443810 toll free usa/canada n. american technical support : 8002829855 toll free usa/canada

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